This section discusses the accuracy of the phase synchronization of the data samples sourced form the legacy eDAQ layers using an eDAQ or eDAQXR system. Legacy eDAQ layer synchronization across channels is accomplished using a single master clock source that drives the data acquisition hardware. The term lag indicates that, in a Time History plot, the data appears later than it should while the term lead indicates that the data appears earlier than it should.
NOTE
Unless otherwise noted, the following discussion and numerical examples assume the Decimal sample rate domain.
Data Synchronization Characterization Method
A ±5000-millivolt triangle function generator waveform is fed in parallel into all channels to be characterized. The frequency of the waveform is set at the sample rate divided by 1000 to yield 1000 sample points per cycle. For each reversal, all data samples that fall between ±2000 millivolts are least squares fit to provide a very accurate measurement of the zero crossing time. The differences in these zero crossing times from one channel to the next represent the data skew from one channel to the next. For each test run, the data skew on at least 200 consecutive reversals is measured and then averaged. At least 3 test runs are performed and the average data skew over the set of test runs is the characterized data skew value.
Analog Channel Phase Synchronization
The EHLS and EBRG channels all employ pre-start periods to compensate for their analog guard filters. In addition to the guard filter skew, there are some other secondary factors that influence data synchronization, such as A/D converter conversion time and transport delays through gain amplifiers.
NOTE
This discussion assumes no digital filtering. Ideally, linear phase digital filters do not result in phase shifts. For the EHLS and EBRG channels, however, the linear phase filters for sample rates at or below 10000 S/s result in a five microsecond lead data skew. The Butterworth digital filters are designed to match their analog equivalents and, therefore, these filters do generate significant phase shifts which, in turn, significantly affects phase synchronization across channels.
Following is a table that contains actual data skew characterization test results (in microseconds) for one eDAQ stack. The data in this table is consistent with the data skew times discussed in this section. The first channel on the first EHLS layer was arbitrarily used as the data sync time reference channel. The test covered the first four channels on two EHLS layers and the first four channels on one EBRG layer. Where applicable, the phase synchronization was characterized using three different sample rates for both the Decimal and Binary sample rate domains.
Channel | Sample Rate (S/s) | |||||
---|---|---|---|---|---|---|
25000 | 10000 | 2500 | 32768 | 8192 | 2048 | |
HLSS_1.c01 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
HLSS_1.c02 | 0.37 | 0.37 | 0.37 | 0.37 | 0.40 | 0.38 |
HLSS_1.c03 | -0.09 | -0.10 | -0.05 | -0.09 | -0.07 | -0.06 |
HLSS_1.c04 | -0.08 | -0.09 | -0.09 | -0.09 | -0.07 | -0.05 |
HLSS_2.c01 | 0.11 | 0.14 | 0.21 | 0.10 | 0.15 | 0.05 |
HLSS_2.c02 | 0.16 | 0.17 | 0.19 | 0.15 | 0.23 | 0.16 |
HLSS_2.c03 | 0.12 | 0.14 | 0.17 | 0.11 | 0.16 | 0.11 |
HLSS_2.c04 | 0.31 | 0.32 | 0.37 | 0.30 | 0.33 | 0.30 |
Brg_1.c01 | 1.65 | 1.64 | 1.68 | 1.60 | 1.60 | 1.57 |
Brg_1.c02 | 1.55 | 1.54 | 1.59 | 1.50 | 1.49 | 1.46 |
Brg_1.c03 | 1.42 | 1.42 | 1.45 | 1.38 | 1.37 | 1.38 |
Brg_1.c04 | 1.57 | 1.57 | 1.63 | 1.52 | 1.49 | 1.55 |
EHLS and EBRG Channel Synchronization
For EHLS and EBRG channels, the relative data synchronization across all channels in any given legacy eDAQ layer stack is typically within a few microseconds. All of these channels use the same type of Butterworth 8-pole analog guard filter, which produces a delay of around 42 microseconds (±2 microseconds). The eDAQXR compensates for this delay by using a fixed value of 40 microseconds for the Decimal sample rate domain to pre-start digital data sampling and align the digital data as close as possible to the actual sample rate clock.
Digital Channel Synchronization
The legacy eDAQ EDIO digital input channels are synchronized to the analog channels as closely as possible. The EDIO layer reads the state of the digital input status register for each digital channel on each edge of the sample clock signal (i.e., when the analog channel A/D converters are read). However, because the digital status registers are updated when a digital input channel changes states, the precise time when a digital input channel changes state is, in general, somewhere in between sample clock edges and hence is not known exactly. Because of this, the digital input channels are expected to lag the analog channels by about half of the sample period on average.