Before assembling a stack of layers, install jumpers correctly on each layer to establish a unique address for each layer when it is connected to a main processor.
Layer Addressing
The eDAQ or eDAQXR-lite stack is configured at the factory with the layer address jumpers properly set.
Follow the guidelines below to reconfigure a stack.
On all compatible layers except the main processor, there is a set of three jumper locations used to assign a physical layer address. Each jumper location consists of two associated pins labeled 1-2, 3-4 or 5-6 where pins 1-2 represent the least significant digit and pins 5-6 represent the most significant in a three-digit binary number. A jumpered pair results in a logical 0. An illustration of all possible logical addresses follows.
All layer address jumper sets are on the side of the bus connector receptacle (i.e., opposite the side with the bus connector bare pins). The jumper is labeled JP1.
To access eDAQ conditioning layers, an eDAQXR EXRCPU must be installed on the top of a layer stack using the eDAQ adapter assembly (1-EXR-E-ADT-2). See eDAQXR EXRCPU installation on eDAQ layers for instructions.
There can be only one main processor in a stack.
A unique hardware ID for each layer is displayed in the web interface. For all layer types that can appear more than once in an eDAQ stack, the hardware IDs have numbered suffixes starting with 1 and are assigned starting with the layer that has the lowest layer address. For example, if there are two EBRG layers in the stack with layer addresses 3 and 4, the layer with address 3 is referenced as Brg_1, and the layer with address 4 is referenced as Brg_2.
The convention for assembling the legacy eDAQ layer stack for an eDAQXR is consistent with the convention used for the eDAQ. For the eDAQXR, this means that the hardware ID suffix decreases as the layer is positioned further away from the EXRCPU layer. In the example above, the EBRG addressed at 3 with hardware ID of Brg_1 is furthest from the EXRCPU layer. It is advised that this convention be followed.
To access eDAQ-lite conditioning layers, an eDAQXR-lite EXRCPU must be installed on the bottom of a layer stack. See eDAQXR-lite EXRLCPU installation on eDAQ-lite layers for instructions.
There can be only one main processor in a stack.
A unique hardware ID for each layer is displayed in the web interface. For all layer types that can appear more than once in an eDAQ-lite stack, the hardware IDs have numbered suffixes starting with 1 and are assigned starting with the layer that has the lowest layer address. For example, if there are two ELBRG layers in the stack with layer addresses 3 and 4, the layer with address 3 is referenced as Brg_1, and the layer with address 4 is referenced as Brg_2.
The convention for assembling the legacy eDAQ-lite layer stack for an eDAQXR-lite is consistent with the convention used for the eDAQ-lite. For the eDAQXR-lite, this means that the hardware ID suffix increases as the layer is positioned further away from the main processor layer. In the example above, the ELBRG addressed at 3 with hardware ID of Brg_1 is closest to the main processor layer. It is advised that this convention be followed.