Compatible layer addressing

Before assembling a stack of layers, install jumpers correctly on each layer to establish a unique address for each layer when it is connected to a main processor.

Layer Addressing

The eDAQ or eDAQXR-lite stack is configured at the factory with the layer address jumpers properly set.

Follow the guidelines below to reconfigure a stack.

On all compatible layers except the main processor, there is a set of three jumper locations used to assign a physical layer address. Each jumper location consists of two associated pins labeled 1-2, 3-4 or 5-6 where pins 1-2 represent the least significant digit and pins 5-6 represent the most significant in a three-digit binary number. A jumpered pair results in a logical 0. An illustration of all possible logical addresses follows.

All layer address jumper sets are on the side of the bus connector receptacle (i.e., opposite the side with the bus connector bare pins). The jumper is labeled JP1.